| 摘要 |
<P>PROBLEM TO BE SOLVED: To realize both high-speed writing and stable rewriting in the DRAM of a high-speed cycle. <P>SOLUTION: A word line and a Y selection line YS1 are simultaneously activated, write data is written from an IO line IOt/b in a selection data line DL1t/b, and the data of a memory cell is read at an adjacent nonselection amplifier. By dividing the source node of the cross couple CC of a sense amplifier connected to each data line pair for each Y selection line, the driving of the source node by a write selection cross coupling is prevented. The write data is written during reading, a high-speed writing operation is realized, and the driving of the source node by the write sense amplifier is prevented. Thus, at the adjacent sense amplifier, a stable reading operation is realized without being influenced by the write sense amplifier. <P>COPYRIGHT: (C)2004,JPO |
