| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor data processor capable of realizing the reduction in power consumption in waiting, the speed-up of interface function, and the reduction in power consumption in operation. <P>SOLUTION: This semiconductor data processor (1) enables the connection of a nonvolatile storage device to the general bus of a host device to take an active state or a standby state in response to the state of the general bus. An internal clock signal (ϕ) is stopped in the standby state, and a substrate bias voltage (vbn, vbp) for suppressing a sub-threshold leak current is applied in the standby state. A central processing unit (2) and the rewritable nonvolatile memory (4) retaining its control program are also the application objects of the substrate bias voltage. When the parallel input and output bit number of data in interface controllers (15 and 16) and a data transfer controller (3) is 2n bit, a one having a data processing unit of n bit or less is adapted as the central processing unit. <P>COPYRIGHT: (C)2004,JPO</p> |
