| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache system capable of appropriately selecting an access mode so that when a CPU carries out a pipeline process for a plurality of instructions, the cache system operates at as low power as possible while preventing a pipeline from waiting for a process, or meeting the requirements for reducing the waiting time for the process. SOLUTION: A branch/prefetch determining part 17, on receiving a branch request signal, sets a cache access mode switch signal at "H" level. Thereby the cache memory 100 operates in a high-power-consumption one-cycle access mode. The branch/prefetch determining part 17, on receiving a prefetch request signal, sets a cache access mode switch signal at "L" level. Thereby the cache memory 100 operates in a low-power-consumption, two-cycle access mode. COPYRIGHT: (C)2004,JPO
|
