| 摘要 |
<P>PROBLEM TO BE SOLVED: To increase the ease of evaluating a system LSI or its installed system. <P>SOLUTION: A CPU control circuit 13 is provided which controls the reset and interrupt of the system LSI which has a plurality of CPUs built in. The CPU control circuit 13 includes a strap take-in circuit 131, a debug control circuit 132, and a bus tracing means 133. Strap information is set in the strap take-in circuit 131 from the outside. The debug control circuit 132 designates one of the CPUs as a target CPU 11 and the other as a debugger CPU 12; outputs a reset/debug interrupt signal to the CPU 12; cancels the resetting of the CPU 11 after the start of the CPU 12; and outputs reset signals also to function blocks 14-16. The bus tracing means 133 takes in information on the CPUs 11, 12 from an interrupt control circuit 134 and a common bus line 17, the interrupt control circuit 134 interrupting the CPUs 11, 12 on receiving inputs of interrupt signals from the function blocks and from the outside and interrupt request signals from the CPU 12. <P>COPYRIGHT: (C)2004,JPO |
