发明名称 METHOD OF MANUFACTURING PRINTED WIRING BOARD
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a method of manufacturing multilayered printed wiring board by which the thickness of lines can be reduced and the accuracy of a wiring pattern can be improved by preventing an etching margin from becoming thick as plating is performed plural times, in a built-up printed wiring board in which components can be mounted on via holes and stacked via holes can also be formed. <P>SOLUTION: Since interlayer connection can be obtained through bumps formed by etching copper foil, the plating performed in the conventional method for conducting via holes become unnecessary and the etching margin becomes thin. Consequently, the method of manufacturing multilayered printed wiring board can be provided by which the thickness of lines can be reduced and the accuracy of the wiring pattern can be improved. <P>COPYRIGHT: (C)2004,JPO</p>
申请公布号 JP2004165545(A) 申请公布日期 2004.06.10
申请号 JP20020331889 申请日期 2002.11.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAWAUCHI KOJI
分类号 H05K1/09;H01L23/12;H05K3/00;H05K3/06;H05K3/40;H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K1/09
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