发明名称 |
Semiconductor memory device and semiconductor integrated circuit |
摘要 |
The present invention provides a semiconductor memory device. In the semiconductor device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors to thereby perform "0" write compensation.
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申请公布号 |
US2004108526(A1) |
申请公布日期 |
2004.06.10 |
申请号 |
US20030722461 |
申请日期 |
2003.11.28 |
申请人 |
TAKAHASHI YASUHIKO;TANAKA TAKAYUKI |
发明人 |
TAKAHASHI YASUHIKO;TANAKA TAKAYUKI |
分类号 |
G11C11/41;G11C11/412;H01L21/8244;H01L27/11;H01L27/12;(IPC1-7):H01L27/10 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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