发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELIEVING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which is provided with a defect relieving circuit which makes it possible to perform relief of timing failure in every specific circuit to be specified by address information and in which relieving efficiency is enhanced while maintaining a high speed operation and a relieving method. SOLUTION: Relief of timing failure in every specific circuit to be specified by address information is realized by providing an AC relieving circuit which relieves operating time margin failure by adjusting selectively the operation timing of the specific circuit in a memory circuit on the basis of the compared coincidence result between the address information set by a first storage means and a selected address signal to the memory circuit which selects either of a plurality of memory cells according to an address signal. COPYRIGHT: (C)2004,JPO
|
申请公布号 |
JP2004164737(A) |
申请公布日期 |
2004.06.10 |
申请号 |
JP20020328815 |
申请日期 |
2002.11.12 |
申请人 |
HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD |
发明人 |
AKASAKI HIROSHI;HASEGAWA MASATOSHI |
分类号 |
G11C29/04;G11C11/401;G11C29/00;(IPC1-7):G11C29/00 |
主分类号 |
G11C29/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|