发明名称 Circuit to detect clock delay and method thereof
摘要 Provided are a circuit and a method of detecting clock delay where the circuit to detect clock delay includes a delay detection circuit and a clock forwarding circuit, the delay detection circuit detects a delay between a predetermined output clock signal and an input clock signal, if the detected delays are identical to one another, the circuit generates an initial parameter corresponding to the delay and if the detected delays are not identical to one another, continuously detects the delay until the detected delays are identical to one another, and generates a reset control signal in response to a system reset signal or a predetermined internal reset signal; the clock forwarding circuit loads and unloads the input data in response to the initial parameter, the circuit to detect clock delay can automatically detect the clock delay necessary for setting the initial parameter of the clock forwarding circuit and reset a master circuit and an external circuit that interfaces with the master circuit, thus performing data transmission without any errors.
申请公布号 US2004109517(A1) 申请公布日期 2004.06.10
申请号 US20040675706 申请日期 2004.01.09
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 SHIN YOUNG-MIN
分类号 G06F1/12;G06F11/00;H03K5/26;H04L7/00;(IPC1-7):H04L7/00 主分类号 G06F1/12
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