| 摘要 |
<p>A selector circuit capable of outputting a signal selected from a plurality of signals with high accuracy. A latch circuit unit (13) generates internal selection control signals (sn, sp) for controlling the selection operation in a selection circuit unit (12). When the levels of the first and second data input signals (IN1, IN2) are not agreed with each other, the selection circuit unit (12) maintains selected state until the levels of signals (IN1, IN2) are agreed with each other according to the internal selection control signals (sn, sp) and does not perform the switching operation based on a selection signal (S).</p> |
