发明名称 |
Multi-level multiprocessor speculation mechanism |
摘要 |
Disclosed is a processor, which reduces issuing of unnecessary barrier operations during instruction processing. The processor comprises an instruction sequencing unit and a load store unit (LSU) that issues a group of memory access requests that precede a barrier instruction in an instruction sequence. The processor also includes a controller, which in response to a determination that all of the memory access requests hit in a cache affiliated with the processor, withholds issuing on an interconnect a barrier operation associated with the barrier instruction. The controller further directs the load store unit to ignore the barrier instruction and complete processing of a next group of memory access requests following the barrier instruction in the instruction sequence without receiving an acknowledgment. |
申请公布号 |
US6748518(B1) |
申请公布日期 |
2004.06.08 |
申请号 |
US20000588483 |
申请日期 |
2000.06.06 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GUTHRIE GUY LYNN;ARIMILLI RAVI KUMAR;DODSON JOHN STEVEN;WILLIAMS DEREK EDWARD |
分类号 |
G06F9/30;G06F9/312;G06F9/38;G06F9/40;G06F13/16;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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