发明名称 |
Hardware loops |
摘要 |
In one embodiment, a programmable processor is configured to support a loop setup instruction. The loop setup instruction may be decoded and a zero offset loop may be detected from the loop setup instruction. The next instruction in the instruction stream may then be immediately issued as a first instruction in a loop. The loop setup instruction may also be used to detect a single instruction loop.
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申请公布号 |
US6748523(B1) |
申请公布日期 |
2004.06.08 |
申请号 |
US20000705217 |
申请日期 |
2000.11.02 |
申请人 |
INTEL CORPORATION;ANALOG DEVICES, INC. |
发明人 |
SINGH RAVI P.;ROTH CHARLES P.;OVERKAMP GREGORY A. |
分类号 |
G06F9/30;G06F9/32;G06F9/38;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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