| 摘要 |
PURPOSE: To reduce the load on an arithmetic processor. CONSTITUTION: In a filter block 1, a filter coefficient to be set in a filter 1 is read out by a filter control input 1 to be supplied to the filter 1 and a delay correction table 1. The delay amount data of the filter 1 read out from the delay correction table 1 are supplied to a delay control part 1, which controls the delay amount of the delay correction part 1 according to the delay amount data. Consequently, the delay amount in the filter block 1 is controlled to a fixed amount regardless of the filter coefficient to be set in the filter 1. A filter block 2 is processed similarly to the filter block 1 and when (Td1+Td2) being a fixed value is set in a delay part 20 from a DPICH, an arithmetic amount is reduced. |
