发明名称 DATA OUTPUT BUFFER CIRCUIT CAPABLE OF CONTROLLING SLEW RATE IN SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE: A data output buffer circuit capable of controlling a slew rate in a semiconductor memory device is provided to improve the operation stability of an output buffer by connecting a switching device to a source of a pre-driver. CONSTITUTION: Pull-up switches(SP0,SP1,SP2), each of which is composed of a resistor or a PMOS(P-channel Metal Oxide Semiconductor), operate in response to at least two pull-up control signals(P0,P1,P2,P3,P4,P5). Pull-down switches(SN0,SN1,SN2,SN3,SN4,SN5) operate in response to at least two pull down control signals(N0,N1,N2,N3,N4,N5) Pre-drivers(MP1,MN1,MP2,MN2) receive power from the pull-up and pull-down switches(SP0,SP1,SP2)(SN0,SN1,SN2,SN3,SN4,SN5) and determine slops of output signals. An output driver operates in response to outputs of the pre-drivers(MP1,MN1,MP2,MN2).
申请公布号 KR20040048036(A) 申请公布日期 2004.06.07
申请号 KR20020075790 申请日期 2002.12.02
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, JUN BAE
分类号 G11C11/40;(IPC1-7):G11C11/40 主分类号 G11C11/40
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