SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT, IN WHICH CELL SIZE IS MINIMIZED

摘要

PURPOSE: A semiconductor memory device and a semiconductor integrated circuit are provided to reduce cell area and to write a logic value '0' properly and to reduce a standby current and also to improve an operation speed. CONSTITUTION: A memory unit is constituted by connecting n-channel MOS transistors(305,306). A source electrode of the n-channel MOS transistors is connected to a low potential power supply voltage(VSS). A drain electrode of the n-channel MOS transistor(305) and a gate electrode of the n-channel MOS transistor(306) become the first node(N3) of the memory unit, and the first node is connected to a bit line(BLT) through a p-channel MOS transistor(301). A drain electrode of the n-channel MOS transistor(306) and a gate electrode of the n-channel MOS transistor(305) become the second node(N4), and the second node is connected to a bit line(BLB) through a p-channel MOS transistor(302). The p-channel MOS transistor(301) is stacked on the n-channel MOS transistor(305), and the p-channel MOS transistor(302) is stacked on the n-channel MOS transistor(306).