LAYOUT SYSTEM FOR SEMICONDUCTOR FLOOR PLAN OF REGISTER RENAMING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To layout a floor plan of a register renaming circuit so as to reduce a chip area on a semiconductor chip. SOLUTION: A system for layouting a floor plan of a register renaming circuit so as to reduce a chip area on a semiconductor chip is provided. The system comprises: a first means for arranging data dependent checkers 108 in a matrix; a second means associated with the first means for disposing a tag assignment logic 122 within one or more layout region such that a channel is defined spacially in one or more rows; and a third means associated with the second means for wiring a further output line into the channel such that the length thereof is minimized. COPYRIGHT: (C)2004,JPO