Verfahren zur Herstellung von einer morphologischen Randstruktur um ein integriertes elektronisches Bauelement zu versiegeln, sowie ein entsprechendes Bauelement

摘要

A process for the formation of a device edge morphological structure (21) for protecting and sealing peripherally an electronic circuit integrated in a major surface (5) of a substrate of semiconductor material (6) calls for formation above an intermediate process structure (11) of a dielectric multilayer (10) comprising a layer of amorphous planarizing material (13) and partial removal of the dielectric multilayer (10) so as to create at least one peripheral termination (25) of the multilayer in the device edge morphological structure (21). In accordance with the present invention removal of the dielectric multilayer (10) requires that the peripheral termination (25) thereof be located in a zone of the intermediate process structure (11) relatively higher than the level of the major surface (5), if compared with adjacent zones of the intermediate structure (11) itself at least internally toward the circuit and in so far as to the device edge morphological structure (21).