发明名称 Voltage level shifter circuit having high speed and low switching power
摘要 A voltage level shifter comprises a plurality of PMOS transistors coupled in series with NMOS transistors to form a plurality of pull-down inverters. When the second voltage level is enabled to connect, the pull-down inverters pull down faster than the pull-down NMOS transistors alone, and thus, the pull-up PMOS transistors pull up immediately to connect the first voltage level to the second voltage level. Thus, the PMOS transistors added to form pull-down inverters improve the switching time and eliminate the kinks in the output voltage.
申请公布号 US2004104756(A1) 申请公布日期 2004.06.03
申请号 US20020309495 申请日期 2002.12.03
申请人 PAYNE JAMES E. 发明人 PAYNE JAMES E.
分类号 H03K3/356;(IPC1-7):H03L5/00 主分类号 H03K3/356
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