发明名称 WIRING PATTERN GENERATION METHOD AND WIRING PATTERN GENERATION DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit applied with a proper wiring delay countermeasure, having desired characteristics. SOLUTION: After deciding arrangement positions of elements mounted in the semiconductor integrated circuit, a distance of a shortest route connecting the elements is found to calculate a provisional delay value, the provisional delay value and a required delay time in each wire are compared, the wiring is classified into cases as this result, positions and the number of used contacts in multilayer wiring are found such that the required delay value is realized, and a wiring pattern is generated on the basis of the found contact positions. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004157663(A) 申请公布日期 2004.06.03
申请号 JP20020321335 申请日期 2002.11.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HARAGUCHI NORIYUKI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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