发明名称 METHOD AND CIRCUIT OF SAMPLING/HOLD
摘要 PROBLEM TO BE SOLVED: To provide a sampling/hold operation circuit which is operated at higher speed and with lower power consumption. SOLUTION: A sampling/hold circuit is provided with a plurality of sampling parts 2-1 to k. Each sampling part has input terminals 1-1 to k and output terminals 3-1 to k, and values received at the input terminal are sampled and these sample values are accumulated, while these accumulated sample values are outputted to the output terminals 3-1 to k. One hold part 6 has an input terminal 5 and an output terminal 7, they are common for a plurality of sampling parts. In a multiplexing part 4, one arbitrary output is connected to an input of the hold part 6 by multiplexing output of a plurality of the sampling parts. The hold part 6 holds a sample value and generates it at an output terminal 7. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004158138(A) 申请公布日期 2004.06.03
申请号 JP20020323757 申请日期 2002.11.07
申请人 TEXAS INSTR JAPAN LTD 发明人 AZUMA KOICHI;MATSUSAKO KYOJI
分类号 G11C27/02;H03K5/00;H03K5/24;H03K17/00;H03M1/00;H03M1/12;(IPC1-7):G11C27/02 主分类号 G11C27/02
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