| 摘要 |
PURPOSE: A data output buffer control circuit is provided to assure an enough spec as to a path disabling a data output buffer, by making a path disabling the data output buffer shorter than a path outputting data. CONSTITUTION: The first multiplexer part(100) outputs one of a rising clock signal and a falling clock signal selectively in response to a CAS latency signal. The second multiplexer part(200) outputs one of the first filtering signal and the second filtering signal selectively in response to the CAS latency signal. A delay part(300) delays an output signal of the second multiplexer part in response to an output signal of the first multiplexer part. A pull-up part(400) pulls up an output port of the delay part to a power supply voltage level in response to a power-up signal and a latch signal and a write/read control signal. And a latch part(500) latches a signal transmitted from the delay part and then generates a data output buffer control signal.
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