发明名称 System and method for reducing computational overhead in a sequenced functional verification system
摘要 The computational load of using a sequencer system and the memory allocation requirements demanded for sequencer operation are reduced in operation with functional models that do not require the services of a sequencer. The computational overhead introduced by the sequencer is reduced, and memory resources for a sequencer are diminished. Functional models that do not require sequencing are created with the same framework as functional models that do require sequencing, while eliminating the sequencer's computational overhead for functional models that do not require sequencing, and allowing functional models that to not require sequencing to be created without allocating the memory required to support the sequencer. Further, both sequenced and un-sequenced functional models coexist in the same sequenced verification framework, permitting the un-sequenced functional models to avoid the computational and memory allocation overhead otherwise incurred by the sequencer.
申请公布号 US6745375(B1) 申请公布日期 2004.06.01
申请号 US19990252174 申请日期 1999.02.18
申请人 CIRRUS LOGIC, INC. 发明人 CARTER HAMILTON B.
分类号 G06F9/45;(IPC1-7):G06F9/45 主分类号 G06F9/45
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