发明名称 SAMPLE AND HOLD CIRCUIT WHICH REDUCES SETTLING TIME
摘要 PROBLEM TO BE SOLVED: To provide a sample and hold circuit in which settling time during a transition time from a hold interval to a sampling interval is reduced. SOLUTION: In a reset state in which a first switch SW1 is closed, a short-circuit switch means SW4 short-circuits first and second electrodes of a hold capacitor CH. In a sample state after the reset state, the first switch SW1 and a second switch SW2 are turned on. In a hold state, a third switch SW3 is turned on. During the transition from the hold state of a previous cycle to the sample state of a next cycle, a short-circuit switch means SW4 short-circuits the capacitor CH and discharges electric charges. Thus, the settling time during the transition time is reduced. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004152329(A) 申请公布日期 2004.05.27
申请号 JP20020313237 申请日期 2002.10.28
申请人 FUJITSU LTD 发明人 NAKAMOTO HIROYUKI
分类号 G11C27/02;H03K17/00;(IPC1-7):G11C27/02 主分类号 G11C27/02
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