| 摘要 |
<p>An interconnect structure (100) having a plurality of input ports and a plurality of output ports, including an input controller (150) which requests permission from predetermined logic within the structure to inject an entire message through two stages of data switches. The request contains only a portion of the address for a message target output with the amount of target output addresses supplied by the input controller (150) depending upon the data rate of the target output port.</p> |
