| 摘要 |
A burst address arithmetic circuit 113 designates an access start address and a burst length based on an input address signal and a data signal, and calculates an access end address based on the access start address and the burst length. Based on an instruction from an internal control circuit 131A, the burst address arithmetic circuit 113 sequentially updates addresses, counts the number of updates, and outputs each of the updated addresses to an address latch circuit 103. When the updated address matches the address end address and also the number of time of update matches the burst length, the burst address arithmetic circuit 113 terminates its operation. When the updated address matches the last column address among column addresses corresponding to one row address, the burst address arithmetic circuit 113 changes the selection/non-selection state of the chip. <IMAGE> |
