Integrated circuit memory devices having efficient multi-row address test capability and methods of operating same

摘要

Integrated circuit memory devices include a word line driver circuit electrically coupled to a plurality of rows of normal memory cells and at least one row of spare memory cells that can be used to replace normal rows having defective cells therein. The word line driver circuit includes a spare word line driver that is electrically coupled to the at least one row of spare memory cells. The spare word line driver includes a programmable address decoder, which generates a spare word line driver enable signal and is responsive to a plurality of row addresses, and a selector switch that is responsive to the spare word line driver enable signal. To assist in performing a multi-row address test, a spare word line driver enable signal precharger is provided that resets the spare word line driver enable signal to a logic level that turns on the selector switch when the memory device is undergoing a multi row address test.