发明名称 |
Synchronous clock generator for integrated circuits |
摘要 |
A synchronous clock generator for an integrated circuit is described in which a delay lock loop circuit may be used to delay a first input signal. A delay circuit is coupled to the delay lock loop circuit and receives a control voltage from the delay lock loop circuit, which is used to delay a second input signal. The first and second input signal may be complimentary.
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申请公布号 |
US6741107(B2) |
申请公布日期 |
2004.05.25 |
申请号 |
US20010802584 |
申请日期 |
2001.03.08 |
申请人 |
INTEL CORPORATION |
发明人 |
BORKAR SHEKHAR Y.;HAYCOCK MATTHEW B.;MOONEY STEPHEN R.;MARTIN AARON K.;KENNEDY JOSEPH T. |
分类号 |
H03L7/081;(IPC1-7):H03L7/00 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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