| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve a soft error resistance of a SRAM by increasing the storage node capacitance of a memory cell of the SRAM. <P>SOLUTION: In a complete CMOS SRAM in which a memory cell is constituted of six pieces of MISFETs, capacitive elements C having stack structures are formed of lower electrodes 16 covering the top of the memory cell, upper electrodes 19, and capacitor insulating films 18 formed between the electrodes 16 and 19. One electrodes (lower electrodes 16) of the elements C are connected to one storage nodes of flip-flop circuits which constitute the memory cell, and the other electrodes (upper electrodes 19) are connected to the other storage nodes of the flip flop circuits. <P>COPYRIGHT: (C)2004,JPO |
