发明名称 |
Composite spacer scheme with low overlapped parasitic capacitance |
摘要 |
A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.
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申请公布号 |
US6737342(B1) |
申请公布日期 |
2004.05.18 |
申请号 |
US20030458141 |
申请日期 |
2003.06.09 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
LEE MING-YI;CHANG CHIEN-HWA |
分类号 |
H01L21/336;H01L29/78;(IPC1-7):H01L21/336;H01L21/22;H01L21/320;H01L21/31 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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