发明名称 |
Schematic organization tool |
摘要 |
A process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process may also be repeated for other predetermined cells which may be selected from a library or created by the user.
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申请公布号 |
US6738957(B2) |
申请公布日期 |
2004.05.18 |
申请号 |
US20010920734 |
申请日期 |
2001.08.03 |
申请人 |
SEMICONDUCTOR INSIGHTS INC. |
发明人 |
GONT VAL;ABT JASON;LAM LARRY;IOUDOVSKI ALEXEI |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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