| 摘要 |
PROBLEM TO BE SOLVED: To enhance reliability of on/off control by providing a first register for temporarily holding a frequency division ratio, and a second register for holding the frequency division ratio inputted at the timing of a phase reference signal from a PLL circuit so that it reflects on a frequency divider thereby preventing generation of incorrect pulse in a switching signal. SOLUTION: A pulse delivered from a PLL circuit 15 is subjected to frequency division at a ration set by a CPU 19. The frequency division ratio is held temporarily in a first register 21 and transferred, at the timing of a phase reference signal 18, to a second register 22 where it is used as the frequency division ratio for a frequency divider 20. A frequency divided pulse is fed to an up/down counter 23 in order to form a triangular carrier wave 25. A signal wave 16 is delivered from the CPU 19 to a voltage command register 26 and compared with the triangular carrier wave 25 by a comparator 27. 1 is outputted if the signal wave 16 is large, otherwise 0 is outputted. That output serves as a gate pulse for on/off controlling a switching element thus controlling the output of an inverter. |
