| 摘要 |
PURPOSE: A multi-pattern analysis apparatus and a multi-pattern analysis method are provided to allow for a high speed processing by using a general purpose processor adopting a hardware logic. CONSTITUTION: A multi-pattern analysis apparatus(100) comprises an offset generator(110) for calculating an offset value from the starting point of the Ethernet packet data input from an external source; an offset and data bus(120) for passing the offset value output from the offset generator and the Ethernet packet data; a plurality of pattern comparators(150) for storing information on the preset offset and size, extracting a plurality of fields from the offset and data bus, and pattern comparing the extracted fields with a predetermined value; one or more Boolean operation processors(140) for performing a logic operation on the resultant value of the pattern comparators in accordance with a predetermined command; and a priority controller(160) for controlling priority of the resultant values output from the Boolean operation processors. |
