发明名称 Information processor and information processing system utilizing interface for synchronizing clock signal
摘要 An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.
申请公布号 US2004093532(A1) 申请公布日期 2004.05.13
申请号 US20030701447 申请日期 2003.11.06
申请人 HOTTA TAKASHI;KURITA KOZABURO;IWAMURA MASAHIRO;MAEJIMA HIDEO;TANAKA SHIGEYA;BANDOH TADAAKI;NAKATSUKA YASUHIRO;KATO KAZUO;SINODA SIN-ICHI 发明人 HOTTA TAKASHI;KURITA KOZABURO;IWAMURA MASAHIRO;MAEJIMA HIDEO;TANAKA SHIGEYA;BANDOH TADAAKI;NAKATSUKA YASUHIRO;KATO KAZUO;SINODA SIN-ICHI
分类号 G06F1/10;H03K5/156;H03L7/18;(IPC1-7):G06F1/04 主分类号 G06F1/10
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