发明名称 |
SIGNAL PROCESSOR, AND ITS METHOD AND ITS PROGRAM |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a signal processor allowing to apply an intermediate signal to input bit length in a calculating means in conducting specified operation by generating and outputting the intermediate signal obtained in a process for the specified operation by means of the calculating means, and then by inputting the intermediate signal to the calculating means for the operation. <P>SOLUTION: A coding device 2 conducts a rounding process so that a horizontal interpolation pixel signal may become 16 bits based on a rounding error adjustment signal run from a rounding control circuit 33 by means of horizontal pixel interpolation operation when a movement prediction/compensation circuit 35 generates an interpolation pixel signal with 1/8 pixel accuracy. Thus, vertical pixel interpolation operation is conducted by using a general-purpose processor having 16-bit input bit length. <P>COPYRIGHT: (C)2004,JPO</p> |
申请公布号 |
JP2004140676(A) |
申请公布日期 |
2004.05.13 |
申请号 |
JP20020304570 |
申请日期 |
2002.10.18 |
申请人 |
SONY CORP |
发明人 |
TSURU DAISUKE;SATO KAZUFUMI;YAGASAKI YOICHI |
分类号 |
H03M7/14;H04N19/103;H04N19/117;H04N19/132;H04N19/137;H04N19/139;H04N19/177;H04N19/186;H04N19/436;H04N19/50;H04N19/51;H04N19/523;H04N19/59;H04N19/625;H04N19/80;H04N19/85;H04N19/91;(IPC1-7):H03M7/14;H04N7/32 |
主分类号 |
H03M7/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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