| 摘要 |
PROBLEM TO BE SOLVED: To provide a data converter capable of significantly reducing the area by decreasing the number of memories, an image generating device using the data converter, and a storage device used by the data converter. SOLUTION: An SRAM103 operates with a double speed clock signal 102 of 300 MHz and other circuit configuration operates with a system clock signal 102 of 150 MHz. An interchangeable circuit 104a converts address signals RA0 and RA1 into serial signals and an interchangeable circuit 104b extracts data OUT0 and OUT 1 corresponding to the signals RA0 and RA1 from serial signal SOUT consisting of data corresponding to the signals RA0 and RA1 output from a multiport SRAM103. The data OUT0 and OUT1 corresponding to the two address signals RA0 and RA1 are read from the multiport SRAM103 in this manner. COPYRIGHT: (C)2004,JPO |
