发明名称 SET-UP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a step-up circuit which is constituted of a transistor of withstand voltage lower than before. SOLUTION: The step-up circuit has a positive step-up circuit 21 which generates positive step-up voltage K×VDD, and a polarity inverting circuit 22 which generates negative step-up voltage -K×VDD with its absolute value equal to it by inverting the polarity of the positive step-up voltage, and the high level of the gate signal generated by a level shift circuit 201 is positive step-up voltage K×VDD. Moreover, the low level of the gate signal is negative step-up voltage -K×VDD or over (0V), the low level of the gate signal generated by a level shift circuit 202 is negative step-up voltage -K×VDD, and the high level is positive step-up voltage K×VDD or under (VDD). COPYRIGHT: (C)2004,JPO
申请公布号 JP2004140892(A) 申请公布日期 2004.05.13
申请号 JP20020301186 申请日期 2002.10.16
申请人 NEC CORP 发明人 NONAKA YOSHIHIRO
分类号 H01L27/04;H01L21/822;H02M3/07;(IPC1-7):H02M3/07 主分类号 H01L27/04
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