发明名称 FERROELECTRIC RANDOM ACCESS MEMORY
摘要 PROBLEM TO BE SOLVED: To stabilize an operation by securing a potential difference margin for a selection/reference bit line. SOLUTION: A dummy cell (a reference potential generating circuit) DC is provided with a paraelectric capacitor DCC1 and a ferroelectric capacitor DCC2. One end of the capacitor DCC1 and one end of the capacitor DCC2 are both connected to a node N1. A dummy plate potential DPL1 is applied to the other end of the capacitor DCC1 and a dummy plate potential DPL2 is applied to the other end of the capacitor DCC2. When data of a memory cell MC are read to a bit line (a selecting bit line) BL1, a reference potential is supplied to a bit line (a reference bit line) BL2 from the cell DC. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004139632(A) 申请公布日期 2004.05.13
申请号 JP20020300522 申请日期 2002.10.15
申请人 TOSHIBA CORP 发明人 ITO YASUO
分类号 G11C11/22;G11C7/02;G11C7/14;(IPC1-7):G11C11/22 主分类号 G11C11/22
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