发明名称 Logic circuit test apparatus and logic circuit test method
摘要 A logic circuit test apparatus for testing a logic circuit having a plurality of input terminals and a plurality of output terminals by inputting original test signals to the input terminals of the logic circuit and testing output signals from the output terminals of the logic circuit, the logic circuit test apparatus including: a common test signal generating circuit which groups the input terminals of the logic circuit on the basis of logic states of original test signals to be applied to the respective input terminals of the logic circuit and outputs common test signals from common test signal output terminals thereof smaller in number than the input terminals of the logic circuit; and an input connection switching circuit which switches connections of the common test signal output terminals of the common test signal generating circuit with the input terminals of the logic circuit so as to convert the common test signals into the original test signals and apply the original test signals to the respective input terminals of the logic circuit.
申请公布号 US2004093542(A1) 申请公布日期 2004.05.13
申请号 US20030668370 申请日期 2003.09.24
申请人 SHARP KABUSHIKI KAISHA 发明人 ISODONO KOJI;ICHIHARA HIDEYUKI
分类号 G01R31/3183;G01R31/28;G01R31/319;(IPC1-7):G01R31/28 主分类号 G01R31/3183
代理机构 代理人
主权项
地址