| 摘要 |
The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. The respective local sense amplifiers for the non-selected global bit lines just read and refresh the respective memory cells resulting in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and are multiplexed. Only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. Thus, respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.
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