发明名称 Concatenation detection across multiple chips
摘要 An apparatus and method for detecting concatenation of payload data for an communication circuit is disclosed, wherein the payload data is dispersed over a first integrated circuit and one or more subsequent integrated circuits. The method and apparatus include determining whether each of the one or more subsequent integrated circuits have all channels therein designated as concatenation slaves, and communicating the determination to the first integrated circuit, the determination indicating that the one or more subsequent integrated circuits. According to an embodiment, the method and apparatus further include coupling the first integrated circuits to the one or more subsequent integrated circuits. The apparatus and method further include detecting concatenation on a first integrated circuit of the one or more integrated circuits, assigning one or more bi-directional ports coupled to the first integrated circuit as an input port, assigning each bi-directional port coupled to the one or more subsequent integrated circuits as output ports, and if any one integrated circuit among the subsequent integrated circuits includes a channel therein designated as a slave channel, providing an active high signal to the output port, the active high signal coupled to the input port of the first integrated circuit.
申请公布号 US6735197(B1) 申请公布日期 2004.05.11
申请号 US20000608097 申请日期 2000.06.30
申请人 CISCO TECHNOLOGY, INC. 发明人 DUSCHATKO DOUGLAS E.;QUIBODEAUX LANE BYRON;HALL ROBERT A.;THURSTON ANDREW J.
分类号 H04J3/16;H04L12/56;(IPC1-7):H04L12/26 主分类号 H04J3/16
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