发明名称 |
Synchronous semiconductor memory device |
摘要 |
A synchronous semiconductor memory device has a memory section which includes a memory cell array having a plurality of memory cells and which is capable of a read operation of reading information from the memory cells according to a read command and a write operation of writing information into the memory cells according to a write command. The synchronous semiconductor memory device further has a command sensing circuit which senses whether a first command inputted in synchronization with an external clock signal is the read command or the write command. The synchronous semiconductor memory device further has a bank timer circuit which, when the command sensing circuit has sensed either the read command or the write command, sets the end time of the restore operation of a row address strobe (RAS) and the start time of the precharge operation of the RAS according to the external clock signal.
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申请公布号 |
US6731559(B2) |
申请公布日期 |
2004.05.04 |
申请号 |
US20020244962 |
申请日期 |
2002.09.17 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
KAWAGUCHI KAZUAKI;OHSHIMA SHIGEO |
分类号 |
G01R31/28;G01R31/3185;G11C7/00;G11C7/10;G11C11/401;G11C11/407;G11C29/12;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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