发明名称 |
Method and apparatus for accumulating partial quotients in a digital processor |
摘要 |
In a digital processor performing division, quotient accumulation apparatus is formed of a set of muxes and a single carry save adder. Partial quotients are accumulated in carry-save form with proper sign extension. Delay of partial quotient bit fragments from one iteration to a following iteration enables the apparatus to limit use to one carry save adder. By enlarging minimal logic, the quotient accumulation apparatus operates at a rate fast enough to support the rate of fast dividers.
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申请公布号 |
US6732135(B1) |
申请公布日期 |
2004.05.04 |
申请号 |
US20000494593 |
申请日期 |
2000.01.31 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
SAMUDRALA SRIDHAR;CLOUSER JOHN D.;GRUNDMANN WILLIAM R. |
分类号 |
G06F7/52;G06F7/535;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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