发明名称 |
Total error multiplier for optimizing read/write channel |
摘要 |
A method and apparatus to optimize a bit error rate for a partial response, maximum likelihood ("PRML") read/write channel is disclosed. A channel margining circuit that is configured to carry out an embodiment for a method of optimizing the bit error rates of a read/write channel is described. The margining circuit derives an interference signal to stress a read/write channel for optimizing the bit error rate. The signal is derived from bit errors inherent with the read/write channel. The circuit reduces the time to optimize the channel by providing an amplified interference signal that increases a bit error rate during optimization.
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申请公布号 |
US6731443(B2) |
申请公布日期 |
2004.05.04 |
申请号 |
US20010896640 |
申请日期 |
2001.06.29 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
BLISS WILLIAM G.;RAE JAMES W. |
分类号 |
G11B20/10;G11B20/18;G11B20/22;(IPC1-7):G11B5/09 |
主分类号 |
G11B20/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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