| 摘要 |
A complimentary non-volatile memory (CNVM) cell includes an n-channel transistor and a p-channel transistor that have drains connected like a CMOS inverter, and that are controlled by a shared floating gate and a shared control gate. The CNVM cell is programmed by band-to-band tunneling (BBT) electrons generated in the source of p-channel transistor, and is erased by BBT holes generated in the source of n-channel transistor (or by back tunneling of electrons from the floating gate). Read out is performed using a select transistor connected to the drains of the n-channel and p-channel transistors.
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