发明名称 Encryption circuit achieving higher operation speed
摘要 An addition and subtraction circuit performs addition and subtraction using a carry-in signal from another operation circuit, and outputs a carry-out signal generated through addition and subtraction to another operation circuit. A right-shift circuit performs right-shift using a shift-in signal from another operation circuit, and outputs a shift-out signal generated through right-shift to another operation circuit. Therefore, even if a data length of operation data is extended, a propagation path for a carry can be shortened, and an operation clock frequency of an encryption circuit can be increased.
申请公布号 US2004081317(A1) 申请公布日期 2004.04.29
申请号 US20030647308 申请日期 2003.08.26
申请人 RENESAS TECHNOLOGY CORP. 发明人 MIYAUCHI SHIGENORI;YAMAGUCHI ATSUO
分类号 G06F5/01;G06F7/72;G09C1/00;(IPC1-7):H04K1/00 主分类号 G06F5/01
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