| 摘要 |
A voltage control circuit for a non-volatile memory (NVM) array or other integrated circuit that uses a comparator circuit, a switch control circuit, and a pair of PMOS switches to selectively couple an output node to the greater of two voltage signals. An output gain provided by the comparator circuit is used to control the coupling process such that the voltage difference needed to switch between the first and second voltage signals is minimized. The high or low comparator output signal is transmitted to the switch control circuit, which utilizes a pair of level shifters to control the pair of PMOS switches, which in turn couple one of the first and second voltage sources to the output node.
|
