Line interface integrated circuit and packet switch

摘要

ATM cells inputted into a physical layer interface (12) are once stored in a cell buffer (24) regardless whether they are ATM cells to be outputted from a switching interface (22) or ATM cells addressed to host CPU (26), and the ATM cells addressed to the host CPU are stored in a temporary RAM (18) at a timing controlled by a scheduler (16). The host CPU 26 read out ATM cells stored in the temporary RAM (18) when necessary. Thereby, no FIFO memory is needed to temporarily store ATM cells addressed to the host CPU (26).