发明名称 ARCHITECTURES FOR DISCRETE WAVELET TRANSFORMS
摘要 <p>A microprocessor structure for performing a discrete wavelet transform operation, said discrete wavelet transform operation comprising decomposition of an input signal comprising a vector of rxk<SUP>m </SUP>input samples, r, k and m being non-zero positive integers, over a specified number of decomposition levels j, where j is an integer in the range 1 to J, starting from a first decomposition level and progressing to a final decomposition level, said microprocessor structure having a number of processing stages, each of said number of processing stages corresponding to a decomposition level j of the discrete wavelet transform operation and being implemented by a number of basic processing elements, the number of basic processing elements implemented in each of said processing stages decreasing by a factor of k from a decomposition level j to a decomposition level j+1.</p>
申请公布号 EP1412911(A1) 申请公布日期 2004.04.28
申请号 EP20020724362 申请日期 2002.05.28
申请人 NOKIA CORPORATION 发明人 GUEVORKIAN, DAVID;LIUHA, PETRI;LAUNIAINEN, AKI, JUHANA;LAPPALAINEN, VILLE
分类号 G06F17/14;G06T1/20;H03M7/30;H04N19/42;(IPC1-7):G06K9/36;G06T9/00;H04N7/26 主分类号 G06F17/14
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