| 摘要 |
A memory test system of the present invention comprises a plurality of memory test units 90A, 90B, . . . , which test memory devices 52 to 56, a host computer (EWS) 10 which evaluates test results of the memory devices 52 to 56, and a common memory unit 12 which connects a plurality of the memory test units 90A, 90B, . . . , to the host computer (EWS) 10. The common memory unit has an interrupt controller (INT CNT) 22. In each of the memory test units 90, a slave processor (MCPU) 40 and a memory for the slave processor (MEM) 14 are provided. MCPU 40 reads memory test results and responses of local processors (RCPU) 42 to 46 which are stored in RMEMs 32 and transfers read data to SMEM 16. MCPU 40 generates an interrupt signal. When all MCPUs 40 generate interrupt signals, INT CNT 22 generates an interrupt signal INT to the EWS 10. The EWS 10 may perform several functions based on the interrupt signal INT.
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