Semiconductor circuit extraction apparatus and method

摘要

A semiconductor circuit extraction apparatus: detects the uppermost wiring layer of a cell; carries out virtual wiring conductor routing on all tracks of a cell-top wiring layer directly overlying the uppermost wiring layer of the cell; extracts parasitic capacitances of all the wiring conductors including those virtually routed; and calculates the delay time of placement/routing data in accordance with the extracted parasitic capacitances to provide highly accurate delay information library data.