发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS FABRICATING METHOD
摘要 PROBLEM TO BE SOLVED: To judge whether a semiconductor integrated circuit device is to go or not to go by detecting partial cut (uncut) of a fuse in the device. SOLUTION: A fuse forming region is provided in a peripheral circuit region within a chip region on a semiconductor substrate and a second layer interconnect line M2 becoming a fuse and a TEG fuse Ft is formed. A plurality of TEG fuses Ft are connected in parallel between the exposed parts of a third layer interconnect line M3, i.e. pad parts Pa and Pb. In a first inspection (P1 inspection), various circuits (peripheral circuits) required for driving a memory cell are tested, e.g. an internal voltage generating circuit is tested for desired operation. If regulation of an output voltage is required, a fuse is cut appropriately and after the output voltage is regulated, a potential is applied across a TEG fuse Ft, which was cut under conditions substantially identical to the cutting conditions of that fuse, through the pad parts Pa and Pb and then a decision is made electrically whether the TEG fuse Ft has been cut or not. If an uncut fuse is present, that chip is judged rejectable. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004127969(A) 申请公布日期 2004.04.22
申请号 JP20020285680 申请日期 2002.09.30
申请人 RENESAS TECHNOLOGY CORP 发明人 OURA TAKEHIRO;SHIGEMATSU KOJI
分类号 H01L21/822;G11C29/00;G11C29/04;H01L21/82;H01L21/8247;H01L27/04;H01L27/10;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L27/10;H01L21/824 主分类号 H01L21/822
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